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- Nov 18, 2002
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Hi,
seit vorgestern ist es offiziel, der neue NVIDIA GeForce Chip heißt "GeForce FX".
Hier sind die Daten zu dem Chip:
GPU:
.13u Manufacturing Process
125 Million Transistors ( 2X GeForce 4)
256-Bit GPU
Flip-Chip BGA Package with copper interconnects
8 Pixel Per Clock (8 Pixel Pipelines)
1 TMU Per Pipe (16 Textures per unit)
> 500MHz Core Clock (Will probably vary depending on model)
350 Million Triangles per Second - 3x The Geometry Performance of a GF4 Ti
AGP8X (2.1GB/s bandwidth)
Memory:
Memory with >1GHz Data Rate (500MHz DDR)
128-Bit "DDRII" Type
128MB & 256MB Memory Capacity
3rd. Generation Lightspeed Memory Architecture
48GB/s Effective bandwidth through the use of compression techniques. (16GB/s actual @ 500MHz)
Other:
Full DX9 Compliance (and more)
64-Bit Floating-Point Color
128-Bit Floating-Point Color
2 x 400MHz Internal RAMDACs
Long Program length for Pixel and Vertex Shading
Conditional Execution for both Pixel and Vertex
True Data-Dependant at Vertex
Unified Vertex and Pixel Shading instruction set
Unified Driver Architecture
nView 2.0 - Multi-Display Technology
Digital Vibrance Control 3.0
Hier noch ein paar Pics vom Chip:
mfg
ki!!ing scum
seit vorgestern ist es offiziel, der neue NVIDIA GeForce Chip heißt "GeForce FX".
Hier sind die Daten zu dem Chip:
GPU:
.13u Manufacturing Process
125 Million Transistors ( 2X GeForce 4)
256-Bit GPU
Flip-Chip BGA Package with copper interconnects
8 Pixel Per Clock (8 Pixel Pipelines)
1 TMU Per Pipe (16 Textures per unit)
> 500MHz Core Clock (Will probably vary depending on model)
350 Million Triangles per Second - 3x The Geometry Performance of a GF4 Ti
AGP8X (2.1GB/s bandwidth)
Memory:
Memory with >1GHz Data Rate (500MHz DDR)
128-Bit "DDRII" Type
128MB & 256MB Memory Capacity
3rd. Generation Lightspeed Memory Architecture
48GB/s Effective bandwidth through the use of compression techniques. (16GB/s actual @ 500MHz)
Other:
Full DX9 Compliance (and more)
64-Bit Floating-Point Color
128-Bit Floating-Point Color
2 x 400MHz Internal RAMDACs
Long Program length for Pixel and Vertex Shading
Conditional Execution for both Pixel and Vertex
True Data-Dependant at Vertex
Unified Vertex and Pixel Shading instruction set
Unified Driver Architecture
nView 2.0 - Multi-Display Technology
Digital Vibrance Control 3.0
Hier noch ein paar Pics vom Chip:
mfg
ki!!ing scum
